// Copyright 2018 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

#pragma once

#define HHI_MIPI_CNTL0                                      (0x000 << 2)
#define HHI_MIPI_CNTL1                                      (0x001 << 2)
#define HHI_MIPI_CNTL2                                      (0x002 << 2)
#define HHI_MIPI_STS                                        (0x003 << 2)
#define HHI_CHECK_CLK_RESULT                                (0x004 << 2)
#define HHI_GP0_PLL_CNTL0                                   (0x010 << 2)
#define HHI_GP0_PLL_CNTL1                                   (0x011 << 2)
#define HHI_GP0_PLL_CNTL2                                   (0x012 << 2)
#define HHI_GP0_PLL_CNTL3                                   (0x013 << 2)
#define HHI_GP0_PLL_CNTL4                                   (0x014 << 2)
#define HHI_GP0_PLL_CNTL5                                   (0x015 << 2)
#define HHI_GP0_PLL_CNTL6                                   (0x016 << 2)
#define HHI_GP0_PLL_STS                                     (0x017 << 2)
#define HHI_PCIE_PLL_CNTL0                                  (0x026 << 2)
#define HHI_PCIE_PLL_CNTL1                                  (0x027 << 2)
#define HHI_PCIE_PLL_CNTL2                                  (0x028 << 2)
#define HHI_PCIE_PLL_CNTL3                                  (0x029 << 2)
#define HHI_PCIE_PLL_CNTL4                                  (0x02a << 2)
#define HHI_PCIE_PLL_CNTL5                                  (0x02b << 2)
#define HHI_PCIE_PLL_STS                                    (0x02c << 2)
#define HHI_XTAL_DIVN_CNTL                                  (0x02f << 2)
#define HHI_GCLK2_MPEG0                                     (0x030 << 2)
#define HHI_GCLK2_MPEG1                                     (0x031 << 2)
#define HHI_GCLK2_MPEG2                                     (0x032 << 2)
#define HHI_GCLK2_OTHER                                     (0x034 << 2)
#define HHI_HIFI_PLL_CNTL0                                  (0x036 << 2)
#define HHI_HIFI_PLL_CNTL1                                  (0x037 << 2)
#define HHI_HIFI_PLL_CNTL2                                  (0x038 << 2)
#define HHI_HIFI_PLL_CNTL3                                  (0x039 << 2)
#define HHI_HIFI_PLL_CNTL4                                  (0x03a << 2)
#define HHI_HIFI_PLL_CNTL5                                  (0x03b << 2)
#define HHI_HIFI_PLL_CNTL6                                  (0x03c << 2)
#define HHI_HIFI_PLL_STS                                    (0x03d << 2)
#define HHI_TIMER90K                                        (0x03f << 2)
#define HHI_MEM_PD_REG0                                     (0x040 << 2)
#define HHI_VPU_MEM_PD_REG0                                 (0x041 << 2)
#define HHI_VPU_MEM_PD_REG1                                 (0x042 << 2)
#define HHI_VIID_CLK_DIV                                    (0x04a << 2)
#define HHI_VIID_CLK_CNTL                                   (0x04b << 2)
#define HHI_VPU_MEM_PD_REG2                                 (0x04d << 2)
#define HHI_GCLK_LOCK                                       (0x04f << 2)
#define HHI_GCLK_MPEG0                                      (0x050 << 2)
#define HHI_GCLK_MPEG1                                      (0x051 << 2)
#define HHI_GCLK_MPEG2                                      (0x052 << 2)
#define HHI_GCLK_OTHER                                      (0x054 << 2)
#define HHI_GCLK_SP_MPEG                                    (0x055 << 2)
#define HHI_SYS_CPU_CLK_CNTL1                               (0x057 << 2)
#define HHI_SYS_CPU_RESET_CNTL                              (0x058 << 2)
#define HHI_VID_CLK_DIV                                     (0x059 << 2)
#define HHI_MPEG_CLK_CNTL                                   (0x05d << 2)
#define HHI_VID_CLK_CNTL                                    (0x05f << 2)
#define HHI_TS_CLK_CNTL                                     (0x064 << 2)
#define HHI_VID_CLK_CNTL2                                   (0x065 << 2)
#define HHI_SYS_CPU_CLK_CNTL                                (0x067 << 2)
#define HHI_VID_PLL_CLK_DIV                                 (0x068 << 2)
#define HHI_MALI_CLK_CNTL                                   (0x06c << 2)
#define HHI_VPU_CLKC_CNTL                                   (0x06d << 2)
#define HHI_VPU_CLK_CNTL                                    (0x06f << 2)
#define HHI_HDMI_CLK_CNTL                                   (0x073 << 2)
#define HHI_ETH_CLK_CNTL                                    (0x076 << 2)
#define HHI_VDEC_CLK_CNTL                                   (0x078 << 2)
#define HHI_VDEC2_CLK_CNTL                                  (0x079 << 2)
#define HHI_VDEC3_CLK_CNTL                                  (0x07a << 2)
#define HHI_VDEC4_CLK_CNTL                                  (0x07b << 2)
#define HHI_HDCP22_CLK_CNTL                                 (0x07c << 2)
#define HHI_VAPBCLK_CNTL                                    (0x07d << 2)
#define HHI_VPU_CLKB_CNTL                                   (0x083 << 2)
#define HHI_GEN_CLK_CNTL                                    (0x08a << 2)
#define HHI_VDIN_MEAS_CLK_CNTL                              (0x094 << 2)
#define HHI_MIPIDSI_PHY_CLK_CNTL                            (0x095 << 2)
#define HHI_NAND_CLK_CNTL                                   (0x097 << 2)
#define HHI_SD_EMMC_CLK_CNTL                                (0x099 << 2)
#define HHI_WAVE420L_CLK_CNTL                               (0x09a << 2)
#define HHI_WAVE420L_CLK_CNTL2                              (0x09b << 2)
#define HHI_MPLL_CNTL0                                      (0x09e << 2)
#define HHI_MPLL_CNTL1                                      (0x09f << 2)
#define HHI_MPLL_CNTL2                                      (0x0a0 << 2)
#define HHI_MPLL_CNTL3                                      (0x0a1 << 2)
#define HHI_MPLL_CNTL4                                      (0x0a2 << 2)
#define HHI_MPLL_CNTL5                                      (0x0a3 << 2)
#define HHI_MPLL_CNTL6                                      (0x0a4 << 2)
#define HHI_MPLL_CNTL7                                      (0x0a5 << 2)
#define HHI_MPLL_CNTL8                                      (0x0a6 << 2)
#define HHI_MPLL_STS                                        (0x0a7 << 2)
#define HHI_FIX_PLL_CNTL0                                   (0x0a8 << 2)
#define HHI_FIX_PLL_CNTL1                                   (0x0a9 << 2)
#define HHI_FIX_PLL_CNTL2                                   (0x0aa << 2)
#define HHI_FIX_PLL_CNTL3                                   (0x0ab << 2)
#define HHI_FIX_PLL_CNTL4                                   (0x0ac << 2)
#define HHI_FIX_PLL_CNTL5                                   (0x0ad << 2)
#define HHI_FIX_PLL_CNTL6                                   (0x0ae << 2)
#define HHI_FIX_PLL_STS                                     (0x0af << 2)
#define HHI_VDAC_CNTL0                                      (0x0bb << 2)
#define HHI_VDAC_CNTL1                                      (0x0bc << 2)
#define HHI_SYS_PLL_CNTL0                                   (0x0bd << 2)
#define HHI_SYS_PLL_CNTL1                                   (0x0be << 2)
#define HHI_SYS_PLL_CNTL2                                   (0x0bf << 2)
#define HHI_SYS_PLL_CNTL3                                   (0x0c0 << 2)
#define HHI_SYS_PLL_CNTL4                                   (0x0c1 << 2)
#define HHI_SYS_PLL_CNTL5                                   (0x0c2 << 2)
#define HHI_SYS_PLL_CNTL6                                   (0x0c3 << 2)
#define HHI_SYS_PLL_STS                                     (0x0c4 << 2)
#define HHI_HDMI_PLL_CNTL0                                  (0x0c8 << 2)
#define HHI_HDMI_PLL_CNTL1                                  (0x0c9 << 2)
#define HHI_HDMI_PLL_CNTL2                                  (0x0ca << 2)
#define HHI_HDMI_PLL_CNTL3                                  (0x0cb << 2)
#define HHI_HDMI_PLL_CNTL4                                  (0x0cc << 2)
#define HHI_HDMI_PLL_CNTL5                                  (0x0cd << 2)
#define HHI_HDMI_PLL_CNTL6                                  (0x0ce << 2)
#define HHI_HDMI_PLL_STS                                    (0x0cf << 2)
#define HHI_HDMI_PHY_CNTL0                                  (0x0e8 << 2)
#define HHI_HDMI_PHY_CNTL1                                  (0x0e9 << 2)
#define HHI_HDMI_PHY_CNTL2                                  (0x0ea << 2)
#define HHI_HDMI_PHY_CNTL3                                  (0x0eb << 2)
#define HHI_HDMI_PHY_CNTL4                                  (0x0ec << 2)
#define HHI_HDMI_PHY_CNTL5                                  (0x0ed << 2)
#define HHI_HDMI_PHY_STATUS                                 (0x0ee << 2)
#define HHI_VID_LOCK_CLK_CNTL                               (0x0f2 << 2)
#define HHI_AXI_PIPEL_CNTL                                  (0x0f4 << 2)
#define HHI_BT656_CLK_CNTL                                  (0x0f5 << 2)
#define HHI_CDAC_CLK_CNTL                                   (0x0f6 << 2)
#define HHI_SPICC_CLK_CNTL                                  (0x0f7 << 2)


#define ENCL_TCON_INVERT_CTL                                (0x1bfd << 2)
#define ENCL_SYNC_LINE_LENGTH                               (0x1c4c << 2)
#define ENCL_SYNC_PIXEL_EN                                  (0x1c4d << 2)
#define ENCL_SYNC_TO_LINE_EN                                (0x1c4e << 2)
#define ENCL_SYNC_TO_PIXEL                                  (0x1c4f << 2)
#define ENCL_VFIFO2VD_CTL                                   (0x1c90 << 2)
#define ENCL_VFIFO2VD_PIXEL_START                           (0x1c91 << 2)
#define ENCL_VFIFO2VD_PIXEL_END                             (0x1c92 << 2)
#define ENCL_VFIFO2VD_LINE_TOP_START                        (0x1c93 << 2)
#define ENCL_VFIFO2VD_LINE_TOP_END                          (0x1c94 << 2)
#define ENCL_VFIFO2VD_LINE_BOT_START                        (0x1c95 << 2)
#define ENCL_VFIFO2VD_LINE_BOT_END                          (0x1c96 << 2)
#define ENCL_VFIFO2VD_CTL2                                  (0x1c97 << 2)
#define ENCL_TST_EN                                         (0x1c98 << 2)
#define ENCL_TST_MDSEL                                      (0x1c99 << 2)
#define ENCL_TST_Y                                          (0x1c9a << 2)
#define ENCL_TST_CB                                         (0x1c9b << 2)
#define ENCL_TST_CR                                         (0x1c9c << 2)
#define ENCL_TST_CLRBAR_STRT                                (0x1c9d << 2)
#define ENCL_TST_CLRBAR_WIDTH                               (0x1c9e << 2)
#define ENCL_TST_VDCNT_STSET                                (0x1c9f << 2)
#define ENCL_VIDEO_EN                                       (0x1ca0 << 2)
#define ENCL_VIDEO_Y_SCL                                    (0x1ca1 << 2)
#define ENCL_VIDEO_PB_SCL                                   (0x1ca2 << 2)
#define ENCL_VIDEO_PR_SCL                                   (0x1ca3 << 2)
#define ENCL_VIDEO_Y_OFFST                                  (0x1ca4 << 2)
#define ENCL_VIDEO_PB_OFFST                                 (0x1ca5 << 2)
#define ENCL_VIDEO_PR_OFFST                                 (0x1ca6 << 2)
#define ENCL_VIDEO_MODE                                     (0x1ca7 << 2)
#define ENCL_VIDEO_MODE_ADV                                 (0x1ca8 << 2)
#define ENCL_DBG_PX_RST                                     (0x1ca9 << 2)
#define ENCL_DBG_LN_RST                                     (0x1caa << 2)
#define ENCL_DBG_PX_INT                                     (0x1cab << 2)
#define ENCL_DBG_LN_INT                                     (0x1cac << 2)
#define ENCL_VIDEO_YFP1_HTIME                               (0x1cad << 2)
#define ENCL_VIDEO_YFP2_HTIME                               (0x1cae << 2)
#define ENCL_VIDEO_YC_DLY                                   (0x1caf << 2)
#define ENCL_VIDEO_MAX_PXCNT                                (0x1cb0 << 2)
#define ENCL_VIDEO_HAVON_END                                (0x1cb1 << 2)
#define ENCL_VIDEO_HAVON_BEGIN                              (0x1cb2 << 2)
#define ENCL_VIDEO_VAVON_ELINE                              (0x1cb3 << 2)
#define ENCL_VIDEO_VAVON_BLINE                              (0x1cb4 << 2)
#define ENCL_VIDEO_HSO_BEGIN                                (0x1cb5 << 2)
#define ENCL_VIDEO_HSO_END                                  (0x1cb6 << 2)
#define ENCL_VIDEO_VSO_BEGIN                                (0x1cb7 << 2)
#define ENCL_VIDEO_VSO_END                                  (0x1cb8 << 2)
#define ENCL_VIDEO_VSO_BLINE                                (0x1cb9 << 2)
#define ENCL_VIDEO_VSO_ELINE                                (0x1cba << 2)
#define ENCL_VIDEO_MAX_LNCNT                                (0x1cbb << 2)
#define ENCL_VIDEO_BLANKY_VAL                               (0x1cbc << 2)
#define ENCL_VIDEO_BLANKPB_VAL                              (0x1cbd << 2)
#define ENCL_VIDEO_BLANKPR_VAL                              (0x1cbe << 2)
#define ENCL_VIDEO_HOFFST                                   (0x1cbf << 2)
#define ENCL_VIDEO_VOFFST                                   (0x1cc0 << 2)
#define ENCL_VIDEO_RGB_CTRL                                 (0x1cc1 << 2)
#define ENCL_VIDEO_FILT_CTRL                                (0x1cc2 << 2)
#define ENCL_VIDEO_OFLD_VPEQ_OFST                           (0x1cc3 << 2)
#define ENCL_VIDEO_OFLD_VOAV_OFST                           (0x1cc4 << 2)
#define ENCL_VIDEO_MATRIX_CB                                (0x1cc5 << 2)
#define ENCL_VIDEO_MATRIX_CR                                (0x1cc6 << 2)
#define ENCL_VIDEO_RGBIN_CTRL                               (0x1cc7 << 2)
#define ENCL_MAX_LINE_SWITCH_POINT                          (0x1cc8 << 2)
#define ENCL_DACSEL_0                                       (0x1cc9 << 2)
#define ENCL_DACSEL_1                                       (0x1cca << 2)
#define ENCL_INFO_READ                                      (0x271f << 2)

#define VPU_VIU_VENC_MUX_CTRL                               (0x271a << 2)
#define VPU_HDMI_SETTING                                    (0x271b << 2)
#define VPU_HDMI_DATA_OVR                                   (0x2727 << 2)
#define VPU_HDMI_FMT_CTRL                                   (0x2743 << 2)

#define L_GAMMA_CNTL_PORT                                   (0x1400 << 2)
#define L_GAMMA_DATA_PORT                                   (0x1401 << 2)
#define L_GAMMA_ADDR_PORT                                   (0x1402 << 2)
#define L_GAMMA_VCOM_HSWITCH_ADDR                           (0x1403 << 2)
#define L_RGB_BASE_ADDR                                     (0x1405 << 2)
#define L_RGB_COEFF_ADDR                                    (0x1406 << 2)
#define L_POL_CNTL_ADDR                                     (0x1407 << 2)
#define L_DITH_CNTL_ADDR                                    (0x1408 << 2)
#define L_GAMMA_PROBE_CTRL                                  (0x1409 << 2)
#define L_GAMMA_PROBE_COLOR_L                               (0x140a << 2)
#define L_GAMMA_PROBE_COLOR_H                               (0x140b << 2)
#define L_GAMMA_PROBE_HL_COLOR                              (0x140c << 2)
#define L_GAMMA_PROBE_POS_X                                 (0x140d << 2)
#define L_GAMMA_PROBE_POS_Y                                 (0x140e << 2)
#define L_STH1_HS_ADDR                                      (0x1410 << 2)
#define L_STH1_HE_ADDR                                      (0x1411 << 2)
#define L_STH1_VS_ADDR                                      (0x1412 << 2)
#define L_STH1_VE_ADDR                                      (0x1413 << 2)
#define L_STH2_HS_ADDR                                      (0x1414 << 2)
#define L_STH2_HE_ADDR                                      (0x1415 << 2)
#define L_STH2_VS_ADDR                                      (0x1416 << 2)
#define L_STH2_VE_ADDR                                      (0x1417 << 2)
#define L_OEH_HS_ADDR                                       (0x1418 << 2)
#define L_OEH_HE_ADDR                                       (0x1419 << 2)
#define L_OEH_VS_ADDR                                       (0x141a << 2)
#define L_OEH_VE_ADDR                                       (0x141b << 2)
#define L_VCOM_HSWITCH_ADDR                                 (0x141c << 2)
#define L_VCOM_VS_ADDR                                      (0x141d << 2)
#define L_VCOM_VE_ADDR                                      (0x141e << 2)
#define L_CPV1_HS_ADDR                                      (0x141f << 2)
#define L_CPV1_HE_ADDR                                      (0x1420 << 2)
#define L_CPV1_VS_ADDR                                      (0x1421 << 2)
#define L_CPV1_VE_ADDR                                      (0x1422 << 2)
#define L_CPV2_HS_ADDR                                      (0x1423 << 2)
#define L_CPV2_HE_ADDR                                      (0x1424 << 2)
#define L_CPV2_VS_ADDR                                      (0x1425 << 2)
#define L_CPV2_VE_ADDR                                      (0x1426 << 2)
#define L_STV1_HS_ADDR                                      (0x1427 << 2)
#define L_STV1_HE_ADDR                                      (0x1428 << 2)
#define L_STV1_VS_ADDR                                      (0x1429 << 2)
#define L_STV1_VE_ADDR                                      (0x142a << 2)
#define L_STV2_HS_ADDR                                      (0x142b << 2)
#define L_STV2_HE_ADDR                                      (0x142c << 2)
#define L_STV2_VS_ADDR                                      (0x142d << 2)
#define L_STV2_VE_ADDR                                      (0x142e << 2)
#define L_OEV1_HS_ADDR                                      (0x142f << 2)
#define L_OEV1_HE_ADDR                                      (0x1430 << 2)
#define L_OEV1_VS_ADDR                                      (0x1431 << 2)
#define L_OEV1_VE_ADDR                                      (0x1432 << 2)
#define L_OEV2_HS_ADDR                                      (0x1433 << 2)
#define L_OEV2_HE_ADDR                                      (0x1434 << 2)
#define L_OEV2_VS_ADDR                                      (0x1435 << 2)
#define L_OEV2_VE_ADDR                                      (0x1436 << 2)
#define L_OEV3_HS_ADDR                                      (0x1437 << 2)
#define L_OEV3_HE_ADDR                                      (0x1438 << 2)
#define L_OEV3_VS_ADDR                                      (0x1439 << 2)
#define L_OEV3_VE_ADDR                                      (0x143a << 2)
#define L_LCD_PWR_ADDR                                      (0x143b << 2)
#define L_LCD_PWM0_LO_ADDR                                  (0x143c << 2)
#define L_LCD_PWM0_HI_ADDR                                  (0x143d << 2)
#define L_LCD_PWM1_LO_ADDR                                  (0x143e << 2)
#define L_LCD_PWM1_HI_ADDR                                  (0x143f << 2)
#define L_INV_CNT_ADDR                                      (0x1440 << 2)
#define L_TCON_MISC_SEL_ADDR                                (0x1441 << 2)
#define L_DUAL_PORT_CNTL_ADDR                               (0x1442 << 2)
#define L_TCON_DOUBLE_CTL                                   (0x1449 << 2)
#define L_TCON_PATTERN_HI                                   (0x144a << 2)
#define L_TCON_PATTERN_LO                                   (0x144b << 2)
#define L_DE_HS_ADDR                                        (0x1451 << 2)
#define L_DE_HE_ADDR                                        (0x1452 << 2)
#define L_DE_VS_ADDR                                        (0x1453 << 2)
#define L_DE_VE_ADDR                                        (0x1454 << 2)
#define L_HSYNC_HS_ADDR                                     (0x1455 << 2)
#define L_HSYNC_HE_ADDR                                     (0x1456 << 2)
#define L_HSYNC_VS_ADDR                                     (0x1457 << 2)
#define L_HSYNC_VE_ADDR                                     (0x1458 << 2)
#define L_VSYNC_HS_ADDR                                     (0x1459 << 2)
#define L_VSYNC_HE_ADDR                                     (0x145a << 2)
#define L_VSYNC_VS_ADDR                                     (0x145b << 2)
#define L_VSYNC_VE_ADDR                                     (0x145c << 2)
#define L_LCD_MCU_CTL                                       (0x145d << 2)

#define VPP_DUMMY_DATA                                      (0x1d00 << 2)
#define VPP_LINE_IN_LENGTH                                  (0x1d01 << 2)
#define VPP_PIC_IN_HEIGHT                                   (0x1d02 << 2)
#define VPP_SCALE_COEF_IDX                                  (0x1d03 << 2)
#define VPP_SCALE_COEF                                      (0x1d04 << 2)
#define VPP_VSC_REGION12_STARTP                             (0x1d05 << 2)
#define VPP_VSC_REGION34_STARTP                             (0x1d06 << 2)
#define VPP_VSC_REGION4_ENDP                                (0x1d07 << 2)
#define VPP_VSC_START_PHASE_STEP                            (0x1d08 << 2)
#define VPP_VSC_REGION0_PHASE_SLOPE                         (0x1d09 << 2)
#define VPP_VSC_REGION1_PHASE_SLOPE                         (0x1d0a << 2)
#define VPP_VSC_REGION3_PHASE_SLOPE                         (0x1d0b << 2)
#define VPP_VSC_REGION4_PHASE_SLOPE                         (0x1d0c << 2)
#define VPP_VSC_PHASE_CTRL                                  (0x1d0d << 2)
#define VPP_VSC_INI_PHASE                                   (0x1d0e << 2)
#define VPP_HSC_REGION12_STARTP                             (0x1d10 << 2)
#define VPP_HSC_REGION34_STARTP                             (0x1d11 << 2)
#define VPP_HSC_REGION4_ENDP                                (0x1d12 << 2)
#define VPP_HSC_START_PHASE_STEP                            (0x1d13 << 2)
#define VPP_HSC_REGION0_PHASE_SLOPE                         (0x1d14 << 2)
#define VPP_HSC_REGION1_PHASE_SLOPE                         (0x1d15 << 2)
#define VPP_HSC_REGION3_PHASE_SLOPE                         (0x1d16 << 2)
#define VPP_HSC_REGION4_PHASE_SLOPE                         (0x1d17 << 2)
#define VPP_HSC_PHASE_CTRL                                  (0x1d18 << 2)
#define VPP_SC_MISC                                         (0x1d19 << 2)
#define VPP_PREBLEND_VD1_H_START_END                        (0x1d1a << 2)
#define VPP_PREBLEND_VD1_V_START_END                        (0x1d1b << 2)
#define VPP_POSTBLEND_VD1_H_START_END                       (0x1d1c << 2)
#define VPP_POSTBLEND_VD1_V_START_END                       (0x1d1d << 2)
#define VPP_BLEND_VD2_H_START_END                           (0x1d1e << 2)
#define VPP_BLEND_VD2_V_START_END                           (0x1d1f << 2)
#define VPP_PREBLEND_H_SIZE                                 (0x1d20 << 2)
#define VPP_POSTBLEND_H_SIZE                                (0x1d21 << 2)
#define VPP_HOLD_LINES                                      (0x1d22 << 2)
#define VPP_BLEND_ONECOLOR_CTRL                             (0x1d23 << 2)
#define VPP_PREBLEND_CURRENT_XY                             (0x1d24 << 2)
#define VPP_POSTBLEND_CURRENT_XY                            (0x1d25 << 2)
#define VPP_MISC                                            (0x1d26 << 2)
#define VPP_OFIFO_SIZE                                      (0x1d27 << 2)
#define VPP_FIFO_STATUS                                     (0x1d28 << 2)
#define VPP_SMOKE_CTRL                                      (0x1d29 << 2)
#define VPP_SMOKE1_VAL                                      (0x1d2a << 2)
#define VPP_SMOKE2_VAL                                      (0x1d2b << 2)
#define VPP_SMOKE3_VAL                                      (0x1d2c << 2)
#define VPP_SMOKE1_H_START_END                              (0x1d2d << 2)
#define VPP_SMOKE1_V_START_END                              (0x1d2e << 2)
#define VPP_SMOKE2_H_START_END                              (0x1d2f << 2)
#define VPP_SMOKE2_V_START_END                              (0x1d30 << 2)
#define VPP_SMOKE3_H_START_END                              (0x1d31 << 2)
#define VPP_SMOKE3_V_START_END                              (0x1d32 << 2)
#define VPP_SCO_FIFO_CTRL                                   (0x1d33 << 2)
#define VPP_HSC_PHASE_CTRL1                                 (0x1d34 << 2)
#define VPP_HSC_INI_PAT_CTRL                                (0x1d35 << 2)
#define VPP_VADJ_CTRL                                       (0x1d40 << 2)
#define VPP_VADJ1_Y                                         (0x1d41 << 2)
#define VPP_VADJ1_MA_MB                                     (0x1d42 << 2)
#define VPP_VADJ1_MC_MD                                     (0x1d43 << 2)
#define VPP_VADJ2_Y                                         (0x1d44 << 2)
#define VPP_VADJ2_MA_MB                                     (0x1d45 << 2)
#define VPP_VADJ2_MC_MD                                     (0x1d46 << 2)
#define VPP_HSHARP_CTRL                                     (0x1d50 << 2)
#define VPP_HSHARP_LUMA_THRESH01                            (0x1d51 << 2)
#define VPP_HSHARP_LUMA_THRESH23                            (0x1d52 << 2)
#define VPP_HSHARP_CHROMA_THRESH01                          (0x1d53 << 2)
#define VPP_HSHARP_CHROMA_THRESH23                          (0x1d54 << 2)
#define VPP_HSHARP_LUMA_GAIN                                (0x1d55 << 2)
#define VPP_HSHARP_CHROMA_GAIN                              (0x1d56 << 2)
#define VPP_MATRIX_PROBE_COLOR                              (0x1d5c << 2)
#define VPP_MATRIX_PROBE_COLOR1                             (0x1dd7 << 2)
#define VPP_MATRIX_HL_COLOR                                 (0x1d5d << 2)
#define VPP_MATRIX_PROBE_POS                                (0x1d5e << 2)
#define VPP_MATRIX_CTRL                                     (0x1d5f << 2)
#define VPP_MATRIX_COEF00_01                                (0x1d60 << 2)
#define VPP_MATRIX_COEF02_10                                (0x1d61 << 2)
#define VPP_MATRIX_COEF11_12                                (0x1d62 << 2)
#define VPP_MATRIX_COEF20_21                                (0x1d63 << 2)
#define VPP_MATRIX_COEF22                                   (0x1d64 << 2)
#define VPP_MATRIX_OFFSET0_1                                (0x1d65 << 2)
#define VPP_MATRIX_OFFSET2                                  (0x1d66 << 2)
#define VPP_MATRIX_PRE_OFFSET0_1                            (0x1d67 << 2)
#define VPP_MATRIX_PRE_OFFSET2                              (0x1d68 << 2)
#define VPP_DUMMY_DATA1                                     (0x1d69 << 2)
#define VPP_GAINOFF_CTRL0                                   (0x1d6a << 2)
#define VPP_GAINOFF_CTRL1                                   (0x1d6b << 2)
#define VPP_GAINOFF_CTRL2                                   (0x1d6c << 2)
#define VPP_GAINOFF_CTRL3                                   (0x1d6d << 2)
#define VPP_GAINOFF_CTRL4                                   (0x1d6e << 2)
#define VPP_CHROMA_ADDR_PORT                                (0x1d70 << 2)
#define VPP_CHROMA_DATA_PORT                                (0x1d71 << 2)
#define VPP_GCLK_CTRL0                                      (0x1d72 << 2)
#define VPP_GCLK_CTRL1                                      (0x1d73 << 2)
#define VPP_SC_GCLK_CTRL                                    (0x1d74 << 2)
#define VPP_MISC1                                           (0x1d76 << 2)
#define VPP_SRSCL_GCLK_CTRL                                 (0x1d77 << 2)
#define VPP_OSDSR_GCLK_CTRL                                 (0x1d78 << 2)
#define VPP_XVYCC_GCLK_CTRL                                 (0x1d79 << 2)
#define VPP_BLACKEXT_CTRL                                   (0x1d80 << 2)
#define VPP_DNLP_CTRL_00                                    (0x1d81 << 2)
#define VPP_DNLP_CTRL_01                                    (0x1d82 << 2)
#define VPP_DNLP_CTRL_02                                    (0x1d83 << 2)
#define VPP_DNLP_CTRL_03                                    (0x1d84 << 2)
#define VPP_DNLP_CTRL_04                                    (0x1d85 << 2)
#define VPP_DNLP_CTRL_05                                    (0x1d86 << 2)
#define VPP_DNLP_CTRL_06                                    (0x1d87 << 2)
#define VPP_DNLP_CTRL_07                                    (0x1d88 << 2)
#define VPP_DNLP_CTRL_08                                    (0x1d89 << 2)
#define VPP_DNLP_CTRL_09                                    (0x1d8a << 2)
#define VPP_DNLP_CTRL_10                                    (0x1d8b << 2)
#define VPP_DNLP_CTRL_11                                    (0x1d8c << 2)
#define VPP_DNLP_CTRL_12                                    (0x1d8d << 2)
#define VPP_DNLP_CTRL_13                                    (0x1d8e << 2)
#define VPP_DNLP_CTRL_14                                    (0x1d8f << 2)
#define VPP_DNLP_CTRL_15                                    (0x1d90 << 2)
#define VPP_SRSHARP0_CTRL                                   (0x1d91 << 2)
#define VPP_SRSHARP1_CTRL                                   (0x1d92 << 2)
#define VPP_DOLBY_CTRL                                      (0x1d93 << 2)
#define VPP_DAT_CONV_PARA0                                  (0x1d94 << 2)
#define VPP_DAT_CONV_PARA1                                  (0x1d95 << 2)
#define VPP_SYNC_SEL0                                       (0x1d96 << 2)
#define VPP_VADJ1_BLACK_VAL                                 (0x1d97 << 2)
#define VPP_VADJ2_BLACK_VAL                                 (0x1d98 << 2)
#define VPP_BLUE_STRETCH_1                                  (0x1d9c << 2)
#define VPP_BLUE_STRETCH_2                                  (0x1d9d << 2)
#define VPP_BLUE_STRETCH_3                                  (0x1d9e << 2)
#define VPP_CCORING_CTRL                                    (0x1da0 << 2)
#define VPP_VE_ENABLE_CTRL                                  (0x1da1 << 2)
#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH                   (0x1da2 << 2)
#define VPP_VE_DEMO_CENTER_BAR                              (0x1da3 << 2)
#define VPP_VE_H_V_SIZE                                     (0x1da4 << 2)
#define VPP_OUT_H_V_SIZE                                    (0x1da5 << 2)
#define VPP_IN_H_V_SIZE                                     (0x1da6 << 2)
#define VPP_VDO_MEAS_CTRL                                   (0x1da8 << 2)
#define VPP_VDO_MEAS_VS_COUNT_HI                            (0x1da9 << 2)
#define VPP_VDO_MEAS_VS_COUNT_LO                            (0x1daa << 2)
#define VPP_INPUT_CTRL                                      (0x1dab << 2)
#define VPP_CTI_CTRL2                                       (0x1dac << 2)
#define VPP_PEAKING_SAT_THD1                                (0x1dad << 2)
#define VPP_PEAKING_SAT_THD2                                (0x1dae << 2)
#define VPP_PEAKING_SAT_THD3                                (0x1daf << 2)
#define VPP_PEAKING_SAT_THD4                                (0x1db0 << 2)
#define VPP_PEAKING_SAT_THD5                                (0x1db1 << 2)
#define VPP_PEAKING_SAT_THD6                                (0x1db2 << 2)
#define VPP_PEAKING_SAT_THD7                                (0x1db3 << 2)
#define VPP_PEAKING_SAT_THD8                                (0x1db4 << 2)
#define VPP_PEAKING_SAT_THD9                                (0x1db5 << 2)
#define VPP_PEAKING_GAIN_ADD1                               (0x1db6 << 2)
#define VPP_PEAKING_GAIN_ADD2                               (0x1db7 << 2)
#define VPP_PEAKING_DNLP                                    (0x1db8 << 2)
#define VPP_SHARP_DEMO_WIN_CTRL1                            (0x1db9 << 2)
#define VPP_SHARP_DEMO_WIN_CTRL2                            (0x1dba << 2)
#define VPP_FRONT_HLTI_CTRL                                 (0x1dbb << 2)
#define VPP_FRONT_CTI_CTRL                                  (0x1dbc << 2)
#define VPP_FRONT_CTI_CTRL2                                 (0x1dbd << 2)
#define VPP_OSD_VSC_PHASE_STEP                              (0x1dc0 << 2)
#define VPP_OSD_VSC_INI_PHASE                               (0x1dc1 << 2)
#define VPP_OSD_VSC_CTRL0                                   (0x1dc2 << 2)
#define VPP_OSD_HSC_PHASE_STEP                              (0x1dc3 << 2)
#define VPP_OSD_HSC_INI_PHASE                               (0x1dc4 << 2)
#define VPP_OSD_HSC_CTRL0                                   (0x1dc5 << 2)
#define VPP_OSD_HSC_INI_PAT_CTRL                            (0x1dc6 << 2)
#define VPP_OSD_SC_DUMMY_DATA                               (0x1dc7 << 2)
#define VPP_OSD_SC_CTRL0                                    (0x1dc8 << 2)
#define VPP_OSD_SCI_WH_M1                                   (0x1dc9 << 2)
#define VPP_OSD_SCO_H_START_END                             (0x1dca << 2)
#define VPP_OSD_SCO_V_START_END                             (0x1dcb << 2)
#define VPP_OSD_SCALE_COEF_IDX                              (0x1dcc << 2)
#define VPP_OSD_SCALE_COEF                                  (0x1dcd << 2)
#define VPP_INT_LINE_NUM                                    (0x1dce << 2)
#define VPP_XVYCC_MISC                                      (0x1dcf << 2)
#define VPP_HLTI_DN_FLT                                     (0x1dd0 << 2)
#define VPP_HLTI_GAIN                                       (0x1dd1 << 2)
#define VPP_HLTI_PARA                                       (0x1dd2 << 2)
#define VPP_HCTI_DN_FLT                                     (0x1dd3 << 2)
#define VPP_HCTI_GAIN                                       (0x1dd4 << 2)
#define VPP_HCTI_PARA                                       (0x1dd5 << 2)
#define VPP_VCTI_PARA                                       (0x1dd6 << 2)
#define VPP_OFIFO_URG_CTRL                                  (0x1dd8 << 2)
#define VPP_CLIP_MISC0                                      (0x1dd9 << 2)
#define VPP_CLIP_MISC1                                      (0x1dda << 2)
#define VPP_MATRIX_COEF13_14                                (0x1ddb << 2)
#define VPP_MATRIX_COEF23_24                                (0x1ddc << 2)
#define VPP_MATRIX_COEF15_25                                (0x1ddd << 2)
#define VPP_MATRIX_CLIP                                     (0x1dde << 2)
#define VPP_XVYCC_MISC0                                     (0x1ddf << 2)
#define VPP_XVYCC_MISC1                                     (0x1de0 << 2)
#define VPP_VD1_CLIP_MISC0                                  (0x1de1 << 2)
#define VPP_VD1_CLIP_MISC1                                  (0x1de2 << 2)
#define VPP_VD2_CLIP_MISC0                                  (0x1de3 << 2)
#define VPP_VD2_CLIP_MISC1                                  (0x1de4 << 2)
#define VPP_VE_DITHER_CTRL                                  (0x3120 << 2)
#define VPP_VE_DITHER_LUT_1                                 (0x3121 << 2)
#define VPP_VE_DITHER_LUT_2                                 (0x3122 << 2)
#define VPP_VE_DITHER_LUT_3                                 (0x3123 << 2)
#define VPP_VE_DITHER_LUT_4                                 (0x3124 << 2)
#define VPP_VE_DITHER_LUT_5                                 (0x3125 << 2)
#define VPP_VE_DITHER_LUT_6                                 (0x3126 << 2)
#define VPP_VE_DITHER_LUT_7                                 (0x3127 << 2)
#define VPP_VE_DITHER_LUT_8                                 (0x3128 << 2)
#define VPP_VE_DITHER_LUT_9                                 (0x3129 << 2)
#define VPP_VE_DITHER_LUT_10                                (0x312a << 2)
#define VPP_VE_DITHER_LUT_11                                (0x312b << 2)
#define VPP_VE_DITHER_LUT_12                                (0x312c << 2)
#define VPP_OSDSC_DITHER_CTRL                               (0x3130 << 2)
#define VPP_OSDSC_DITHER_LUT_1                              (0x3131 << 2)
#define VPP_OSDSC_DITHER_LUT_2                              (0x3132 << 2)
#define VPP_OSDSC_DITHER_LUT_3                              (0x3133 << 2)
#define VPP_OSDSC_DITHER_LUT_4                              (0x3134 << 2)
#define VPP_OSDSC_DITHER_LUT_5                              (0x3135 << 2)
#define VPP_OSDSC_DITHER_LUT_6                              (0x3136 << 2)
#define VPP_OSDSC_DITHER_LUT_7                              (0x3137 << 2)
#define VPP_OSDSC_DITHER_LUT_8                              (0x3138 << 2)
#define VPP_OSDSC_DITHER_LUT_9                              (0x3139 << 2)
#define VPP_OSDSC_DITHER_LUT_10                             (0x313a << 2)
#define VPP_OSDSC_DITHER_LUT_11                             (0x313b << 2)
#define VPP_OSDSC_DITHER_LUT_12                             (0x313c << 2)
#define VPP_OSDSC_DITHER_LUT_13                             (0x313d << 2)
#define VPP_OSDSC_DITHER_LUT_14                             (0x313e << 2)
#define VPP_OSDSC_DITHER_LUT_15                             (0x313f << 2)
#define VPP_EOTF_CTL                                        (0x31d0 << 2)
#define VPP_EOTF_COEF00_01                                  (0x31d1 << 2)
#define VPP_EOTF_COEF02_10                                  (0x31d2 << 2)
#define VPP_EOTF_COEF11_12                                  (0x31d3 << 2)
#define VPP_EOTF_COEF20_21                                  (0x31d4 << 2)
#define VPP_EOTF_COEF22_RS                                  (0x31d5 << 2)
#define VPP_EOTF_LUT_ADDR_PORT                              (0x31d6 << 2)
#define VPP_EOTF_LUT_DATA_PORT                              (0x31d7 << 2)
#define VPP_EOTF_3X3_OFST_0                                 (0x31d8 << 2)
#define VPP_EOTF_3X3_OFST_1                                 (0x31d9 << 2)

#define VPP_OUT_SATURATE            (1 << 0)

// HHI_MIPI_CNTL0 Register Bit Def
#define MIPI_CNTL0_CMN_REF_GEN_CTRL(x)      (x << 26)
#define MIPI_CNTL0_VREF_SEL(x)              (x << 25)
 #define VREF_SEL_VR                    0
 #define VREF_SEL_VBG                   1
#define MIPI_CNTL0_LREF_SEL(x)              (x << 24)
 #define LREF_SEL_L_ROUT                0
 #define LREF_SEL_LBG                   1
#define MIPI_CNTL0_LBG_EN                   (1 << 23)
#define MIPI_CNTL0_VR_TRIM_CNTL(x)          (x << 16)
#define MIPI_CNTL0_VR_GEN_FROM_LGB_EN       (1 << 3)
#define MIPI_CNTL0_VR_GEN_BY_AVDD18_EN      (1 << 2)

// HHI_MIPI_CNTL1 Register Bit Def
#define MIPI_CNTL1_DSI_VBG_EN               (1 << 16)
#define MIPI_CNTL1_CTL                      (0x2e << 0)

// HHI_MIPI_CNTL2 Register Bit Def
#define MIPI_CNTL2_DEFAULT_VAL              (0x2680fc5a) // 4-lane DSI LINK

// HHI_VIID_CLK_DIV Register Bit Def
#define DAC0_CLK_SEL                        (28)
#define DAC1_CLK_SEL                        (24)
#define DAC2_CLK_SEL                        (20)
#define VCLK2_XD_RST                        (17)
#define VCLK2_XD_EN                         (16)
#define ENCL_CLK_SEL                        (12)
#define VCLK2_XD                            (0)

// HHI_VIID_CLK_CNTL Register Bit Def
#define VCLK2_EN                            (19)
#define VCLK2_CLK_IN_SEL                    (16)
#define VCLK2_SOFT_RST                      (15)
#define VCLK2_DIV12_EN                      (4)
#define VCLK2_DIV6_EN                       (3)
#define VCLK2_DIV4_EN                       (2)
#define VCLK2_DIV2_EN                       (1)
#define VCLK2_DIV1_EN                       (0)

// HHI_VIID_DIVIDER_CNTL Register Bit Def
#define DIV_CLK_IN_EN                       (16)
#define DIV_CLK_SEL                         (15)
#define DIV_POST_TCNT                       (12)
#define DIV_LVDS_CLK_EN                     (11)
#define DIV_LVDS_DIV2                       (10)
#define DIV_POST_SEL                        (8)
#define DIV_POST_SOFT_RST                   (7)
#define DIV_PRE_SEL                         (4)
#define DIV_PRE_SOFT_RST                    (3)
#define DIV_POST_RST                        (1)
#define DIV_PRE_RST                         (0)

// HHI_VID_CLK_DIV Register Bit Def
#define ENCI_CLK_SEL                        (28)
#define ENCP_CLK_SEL                        (24)
#define ENCT_CLK_SEL                        (20)
#define VCLK_XD_RST                         (17)
#define VCLK_XD_EN                          (16)
#define ENCL_CLK_SEL                        (12)
#define VCLK_XD1                            (8)
#define VCLK_XD0                            (0)

// HHI_VID_CLK_CNTL2 Register Bit Def
#define HDMI_TX_PIXEL_GATE_VCLK             (5)
#define VDAC_GATE_VCLK                      (4)
#define ENCL_GATE_VCLK                      (3)
#define ENCP_GATE_VCLK                      (2)
#define ENCT_GATE_VCLK                      (1)
#define ENCI_GATE_VCLK                      (0)

// HHI_HDMI_PHY_CNTL Register Bit Def
#define LCD_PLL_LOCK_HPLL_G12A              (31)
#define LCD_PLL_EN_HPLL_G12A                (28)
#define LCD_PLL_RST_HPLL_G12A               (29)
#define LCD_PLL_OUT_GATE_CTRL_G12A          (25)
#define LCD_PLL_OD3_HPLL_G12A               (20)
#define LCD_PLL_OD2_HPLL_G12A               (18)
#define LCD_PLL_OD1_HPLL_G12A               (16)
#define LCD_PLL_N_HPLL_G12A                 (10)
#define LCD_PLL_M_HPLL_G12A                 (0)

